1. Field of the Invention
This invention relates to an insulated gate type semiconductor device, and particularly to the improvement of the structure of a thin-film insulated gate field effect transistor (TFT) and a method for producing the same.
2. Description of Related Arts
Recently, a thin-film insulated gate field effect transistor (TFT) has been extensively studied. For example, in Japanese Patent Application No. 3-237100 or No. 3-238713 which has been invented by this inventor, et.al., are disclosed a TFT and a method of producing the same in which a gate electrode formed of aluminum is coated therearound with aluminum oxide which is formed by an anodic oxidation method, and a source/drain region is recrystallized by a laser annealing treatment.
The TFT thus formed has been proved to have a more excellent characteristic in comparison with a conventional silicon gate TFT or a TFT having a gate electrode which is formed of metal having high melting point such as tantalum or chrome. However, this excellent characteristic has been unobtainable with high reproducibility.
In addition, in Japanese Patent Application No. 4-30220 or No. 4-38637 which is invented by the inventor, et.al, is disclosed another type TFT and a method for producing the TFT in which a gate electrode formed of aluminum, titanium, chrome, tantalum or silicon is coated therearound with aluminum oxide formed by the anodic oxidation method so that the source/drain is not overlapped with the gate electrode, that is, these elements are formed in an offset state, and the source/drain region is recrystallized by the laser annealing treatment.
The TFT thus formed is also proved to have a more excellent characteristic in comparison with a conventional silicon gate TFT having no offset or a TFT which is provided with a gate electrode formed of metal having high melting point such as tantalum or chrome and is activated by a heat annealing treatment. However, this excellent characteristic has been also unobtainable with high reproducibility. One cause of the low reproducibility resides in the invasion (contamination) of movable ions such as natrium, etc. from the external. The reproducibility is deteriorated by the invasion of natrium from the external, particularly in a process of forming a gate electrode of metal material such as aluminum or the like (using a sputtering method or a electron beam deposition method), and in a subsequent anodic oxidation process. Particularly in the sputtering method, the risk of the invasion (contamination) of natrium ions is large. However, the sputtering method has higher producibility than the electron beam deposition method, and thus its use has been necessarily desirable to reduce a manufacturing cost.
It has been known that natrium is blocked by phosphosilicate glass and also gettered thereby. Therefore, a gate insulating film has been generally formed of phosphosilicate glass. However, it is difficult to form the phosphosilicate glass at a low temperature which is aimed by the inventions as disclosed in the above Patent Applications. In addition, if the formation of the phosphosilicate glass at such a low temperature is attempted, for example by injecting phosphorus into a silicon oxide gate insulating film using an ion doping method, there frequently occurs a problem that a large number of defects occur in the gate insulating film and thus the characteristic of the TFT is rather deteriorated.
In addition, high voltage of 100 to 300 V is required for the anodic oxidation, and thus there is a risk that the gate insulating film is damaged by the high voltage. That is, in the technical scope of the inventions as described above, the gate insulating film is formed on a semiconductor film, and the gate electrode exists on the gate insulating film. In this construction, a voltage occurs between the positively-charged gate electrode and the semiconductor film in a floating state in the anodic oxidation process. Therefore, as the resistance between the gate electrode and an electrolyte is increased in accordance with increase of the thickness of an anodic oxidation film on the gate electrode, the amount of current passing from the gate electrode through the gate insulating film and the semiconductor film to the electrolyte is increased. Accordingly, there occurs a case where the gate electrode is damaged by this current.
Further, in the inventions as described above, aluminum oxide is formed around a gate wiring. The aluminum oxide serves to improve insulation from a wiring layer thereon, and protect the gate electrode in a laser annealing treatment. However, it is difficult to form a contact hole in the aluminum oxide. In addition, when aluminum oxide is etched by a wet etching method which is excellent in producibility, an etchant forcedly etches silicon oxide which is used as an interlayer insulator, and the etching rate of silicon oxide is higher than aluminum oxide. Therefore, a vapor etching method such as a reactive ion etching method is necessarily required to be used.
The TFT is mainly classified into an inverse-stagger type which is well used for an amorphous silicon TFT and a planar type which is well used for a polycrystal silicon TFT. The latter type can have large mobility, so that it is expected to be available for a wide use. Such a TFT is mainly used for a large-area circuit which has not been covered by a conventional monocrystal IC. The conventional planar type of TFT has the same construction as the conventional monocrystal IC as shown in FIG. 12.
As is apparent from FIG. 12, the planar type of TFT is so designed as to be very flat over its whole body. This structure is very favorable for a case where it is used as an active element for a liquid crystal display device. This is because in the liquid crystal display device, the thickness of a liquid crystal layer is about 5 to 6 xcexcm, and it is required to control the thickness with accuracy of xc2x10.1 xcexcm as a whole. Therefore, an element structure having high unevenness (a large number of recesses and projections) causes ununiformity of electric field, so that not only the characteristic of the element is deteriorated, but also the element itself suffers a mechanical damage.
The element structure as shown in FIG. 12 is a general one for the planar type of TFT. The structure and the method for producing the TFT will be briefly described.
A silicon oxide layer 902 serving as a sealer is formed on an insulating substrate 901 such as a glass substrate, and a semiconductor region 903 is formed on the silicon oxide layer 902. Further, a gate insulating film 904 is formed, and then a wiring 905 and a gate electrode 906 are formed of a first metal wiring layer.
Thereafter, an impurity region is formed in the semiconductor region in self-alignment, an interlayer insulator 907 is formed, and then a hole for electrode formation (contact hole) is formed. Subsequently, metal wirings 908 and 909 are formed of a second metal wiring layer. If the TFT is used for a liquid crystal display device, a pixel electrode 910 is formed of transparent conductive material.
As described above, the planar type of TFT having the structure as shown in FIG. 12 is characterized in that unevenness of the structure is low, however, has several problems. The maximum significant problem resides in that a hole is formed in an electrode, and thus unevenness becomes higher at the contact hole portion, so that disconnection or contact failure occurs at the portion. Particularly, an unit part of a large-area circuit in which a TFT is used, has an area of at least 10 times as large as a conventional monocrystal IC, so that it is very difficult to depress the disconnection or contact failure over the whole area. In order to avoid this problem, the contact hole is required to be widened. However, the increase of the size of the contact hole causes enlargement of the element area, and causes reduction in aperture ratio for a liquid crystal display device, for example.
In order to further avoid this problem, a structure as shown in FIG. 11 in which the concept of xe2x80x9ccontact holexe2x80x9d is dismissed and the unevenness at the electrode portion is depressed is proposed. In this structure, there is no interlayer insulator at an electrode portion which is connected to a source/drain of a semiconductor region, and no contact hole is provided. In place of the contact hole, a metal wiring is directly formed. This structure enables the contact area of the contact to be increased, and the contact failure at the portion is greatly reduced. This is based on the fact that there is little step at the contact portion.
The structure as shown in FIG. 11 and the method of producing the structure will be briefly described.
First, a silicon oxide layer 802 serving as a sealer is formed on a substrate 801. Subsequently, a semiconductor region 803 is formed, and then a gate insulating film 804 is formed. Further, a wiring 805 and a gate electrode 806 are formed of a first metal layer, and an impurity region is formed in self-alignment using the gate electrode as a mask, thereafter, an interlayer insulator 807 being formed. The interlayer insulator 807 is not formed at the semiconductor region. For example, after the layer insulating film is formed over the whole surface, the layer insulator at the semiconductor region is removed. At this time, the gate insulating film 804 is also etched. In an extreme manner, no interlayer insulator is formed at portions other than a portion where the first and second metal layers are overlapped with each other. That is, the etching treatment is carried out in self-alignment using the gate electrode 806 and the semiconductor region 803 as a mask together with a photoresist at the portion where wirings are intersected to each other. Thereafter, wirings 808 and 809 are formed of the second metal layer, and contacted to the semiconductor region. For the liquid crystal display device, a transparent electrode 810 is further formed.
In the structure as shown in FIG. 11, there is no contact hole, and thus no contact failure occurs at this portion. However, other problems occur. One problem is that in a process of removing the interlayer insulating film, the etching extends to not only the silicon oxide film 802, but also the substrate. This is liable to occur when the etching process is carried out using the wet etching method providing high producibility. The temperature distribution of the substrate of a large-area substrate is ununiform, and the etching rate of an usual etchant is greatly varied in accordance with minute difference of temperature, so that an over-etched portion occurs when the etching treatment is continued until the etching is completely conducted on the whole portion.
On the other hand, in a dry etching treatment such as a reactive ion etching (RIE), the uniformity of plasma distribution greatly affects the etching rate, and it is difficult to assure uniformity of etching over the whole area of the substrate. Therefore, the larger the area is, the more critical the over-etching problem becomes. For example, as shown, in FIG. 11, there occurs a case where the substrate is etched in depth of d due to an over-etch. This structure has a larger step than the structure as shown in FIG. 12, and thus it is unsuitable not only for the liquid crystal display device, but also for other applications such as a driving circuit for an image sensor, etc.
In addition, even on the same substrate, no over-etch occurs at suitably-etched portions, and thus these portions are not etched as shown above. Therefore, the etching depth is varied with a position on the surface of the substrate, so that a moderate unevenness occurs on the surface of the substrate. This unevenness on the surface of the substrate causes a critical problem for application to the liquid crystal display device.
The over-etching problem is not limited to the above problem. In general, a semiconductor element is formed under an extremely pure atmosphere, and foreign elements such as natrium, etc. are extremely excluded. However, foreign elements are necessarily contaminated in the substrate although contamination amount is varied, and in order to prevent diffusion of the foreign elements in the TFT, these elements are blocked by the silicon oxide film layer serving as a sealer.
However, the above blocking effect of the silicon oxide layer would be lost if the substrate is exposed due to the over-etch as shown in FIG. 11, and thus the foreign elements are diffused through the substrate. The foreign elements contaminate an etching tank for the wet etching treatment, or an etching chamber for the dry etching treatment, for example. Therefore, if the contaminated state is left as it is, the contamination would extend to not only a product concerned, but also other products to be subsequently manufactured. Much labor and long time are required for a cleaning process for removing the foreign elements, and such a special process economically deteriorates this method.
An object of this invention is to provide an insulating gate type of semiconductor device (an insulated gate field effect transistor) and a producing method therefor in which an over-etching phenomenon is depressed to prohibit the diffusion of foreign elements from a substrate and flatness of the device is further improved.
Another object of this invention is to provide the structure of a TFT and a producing method therefore in which invasion of movable ions from an external is prevented, and a contact with aluminum wirings coated with an anodic oxide film is facilitated, and in which breakdown of a gate insulating film is prevented to improve reliability of a device.
In order to attain the above objects, an insulated gate field effect transistor (an insulating gate type of semiconductor device) according to this invention comprises at least a semiconductor layer provided on an insulating substrate, an insulating film layer provided on the semiconductor layer and a gate electrode provided on the insulating layer and comprising aluminum, chromium, titanium, tantalum, silicon, aluminum having added thereto silicon at 0.5 to 3%, an alloy thereof, or a multi-layer thereof, wherein the insulating film layer comprises an aluminum oxide monolayer, a silicon oxide monolayer, a silicon nitride monolayer, a two-layer of an aluminum oxide layer and a silicon nitride layer, a two-layer of an aluminum oxide layer and a silicon oxide layer, a two-layer of a silicon nitride layer and a silicon oxide layer, a two-layer of a phosphosilicate glass layer and a silicon oxide layer, or a three-layer of an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.
A producing method for the insulating gate type of semiconductor device according to this invention comprising the steps of forming a semiconductor region on an insulating substrate, forming on the semiconductor region an insulating film layer comprising an aluminum oxide monolayer, a silicon oxide monolayer, a silicon nitride monolayer, a two-layer of an aluminum oxide layer and a silicon nitride layer, a two-layer of an aluminum oxide layer and a silicon oxide layer, a two-layer of a silicon nitride layer and a silicon oxide layer, a two-layer of a phosphosilicate glass layer and a silicon oxide layer, or a three-layer of an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer, forming on the insulating film layer a metal film (conductor film) mainly formed of aluminum, chromium, titanium, tantalum, silicon, aluminum having added thereto silicon at 0.5 to 3%, an alloy thereof, or a multi-layer thereof, and supplying current to the metal film (conductor film) in an electrolyte to form an oxide layer on the metal film. A current is made to flow through the conductor film in the electrolyte by the supplying step to form a film comprising an oxide of the material of the conductor film on a surface of the conductor film.
According to one aspect of this invention, a silicon nitride film is interposed between an aluminum gate electrode and a gate insulating film. Assuming the composition ratio of silicon in the silicon nitride film to 1, the composition ratio of nitrogen is in a range of 1 to 4/3, preferably in a range of 1.2 to 4/3, and more preferably in a range of 1.25 to 4/3. In addition to nitrogen and silicon, hydrogen or oxygen may be added.
The silicon nitride film serves to block movable ions such as natrium, etc., and thus prevent the movable ions from invading from the gate electrode and other portions into a channel region. In addition, silicon nitride has higher conductivity than silicon oxide which is usually used for the gate insulating film, and thus the silicon nitride film also serves to prevent an excessive voltage from being applied between the gate electrode and the semiconductor region (channel region) beneath the gate electrode, so that breakdown of the gate insulating film is prevented.
Accordingly, the semiconductor region and the gate insulating film are formed, then the silicon nitride film is formed, and then an aluminum electrode is formed to form the gate electrode. The silicon nitride film is also preferable because when the silicon nitride film exists integrally over the whole surface of the substrate during the anodic oxidation of the aluminum electrode, the positive potential is kept to a substantially constant potential over the whole surface of the substrate.
According to another aspect of this invention, in the gate electrode and the wiring extending thereto whose surfaces will be subjected to the anodic oxidation in a subsequent process, a portion thereof which requires contact formation is covered by material which is different from aluminum and has a mask action against the anodic oxidation. As the material is suitably used chrome, gold, titanium, silicon, indium oxide, titanium oxide, indium-titanium oxide, zinc oxide or the like.
At the portion covered by the above material, only the following two cases will occur in the anodic oxidation. That is, an oxide is formed on the surface of the portion, or no new oxide is formed on the surface of the portion. For example, if chrome or titanium is used, the former case will occur. On the other hand, if gold, titanium oxide, indium oxide or the like is used, the latter case will occur.
After the anodic oxidation, only the above material is selectively etched to expose the surface of metal aluminum of the gate wiring. Therefore, a contact hole is easily formed. Further, this invention is also favorable for the anodic oxidation. That is, in the anodic oxidation, all gate electrodes and wirings are required to be connected to one another, and kept to a positive potential. However, when those elements are practically used in a circuit, the circuit never functions if all the gate electrodes and wirings are integrally formed (integrally connected). Therefore, it is necessary that the wirings are cut or broken if occasion demands, and then the wirings are connected to one another again. This technique is typically disclosed in Japanese Patent Application No. 3-348130 which is invented by the inventor of this application, et.al.
In this technique, the following three photolithographic processes are required: (1) formation of gate wirings, (2) patterning of the gate wirings after anodic oxidation, and (3) re-connection of the gate wirings. Particularly in the process (3), the etching of aluminum oxide is difficult as described above, and thus formation of a contact hole is difficult.
However, according to this invention, the above requirement is satisfied by the following three photolithographic processes: (1) formation of gate wirings, (2) formation of wirings for anodic oxidation, and (3) re-connection of the gate wirings. The wirings for anodic oxidation are ones which are used only to supply current for anodic oxidation to a gate electrode for each TFT. These wirings are formed of the material as described above, and thus the etching thereof can be selectively carried out, so that the photolithographic process is unnecessary. In addition, after the wirings for anodic oxidation are removed, the surfaces of the gate wirings are exposed, and thus it is easily carried out to form on the surfaces wirings through which the gate wirings are connected to one another.
According to another aspect of this invention, an aluminum oxide or silicon nitride layer is provided as an etching stopper layer on the substrate to prevent the over-etching. The aluminum oxide or silicon nitride layer may be provided between the substrate and the silicon oxide layer serving as the sealer on the substrate, or between the gate oxide film and the gate electrode. In this case, the interlayer insulator is etched before the electrode of the TFT is formed, however, the etching is stopped at the aluminum oxide or silicon nitride layer. That is, according to this invention, the etching can be uniformly carried out over the whole portion of the substrate. Of course, the possibility of occurrence of the contact failure, etc. is lowered because no contact hole exists. This will be described with reference to FIG. 10.
FIG. 10 shows a typical embodiment of this invention. In this embodiment, the aluminum oxide or silicon nitride film of this invention is formed between the gate insulating film and the gate electrode. In this case, the relationship in composition ratio between nitrogen and silicon in silicon nitride is as follows. Assuming the composition ratio of silicon to 1, the composition ratio of nitrogen is in a range of 1 to 4/3, preferably in a range of 1.2 to 4/3, and more preferably in a range of 1.25 to 4/3. For aluminum oxide, assuming aluminum to 1, oxygen is preferably in range of 1.4 to 1.5. The aluminum oxide or silicon nitride layer is required to have such a thickness that it can endure the etching. For example, in the wet etching treatment of silicon oxide, the etching of aluminum oxide or silicon nitride can be depressed at an extremely low level, whereas in the dry etching treatment such as RIE, a suitable thickness, for example, 50 to 1000 nm thickness is required for aluminum oxide or silicon nitride because a selection ratio of aluminum oxide or silicon nitride is not negligible. However, in the case where the aluminum oxide or silicon nitride layer is disposed between the gate electrode and the gate insulating film as shown in FIG. 10, an excessively thick aluminum oxide or silicon nitride layer obstructs the operation of the, TFT, and thus the thickness of the aluminum oxide or silicon nitride layer is set to a suitable one, for example, 2 to 50 nm.
The structure of the TFT as shown in FIG. 10 and the producing method therefore will be briefly described.
A reference numeral 701 represents a substrate, and a reference numeral 702 represents a silicon nitride layer (first silicon nitride layer) which is formed to prevent diffusion of foreign elements of the substrate into the TFT. A reference numeral 703 represents a silicon oxide layer serving as a sealer for preventing back-leak of the TFT. A reference numeral 704 represents a semiconductor region, and after the formation of the semiconductor region 704, a gate insulating film 705 and the aluminum oxide or silicon nitride layer (second aluminum oxide or silicon nitride layer) are formed. Thereafter, a wiring 707 and a gate electrode 708 are formed of a first metal layer. In this embodiment, an oxide is formed by the anodic oxidation method around the wiring and the electrode to strengthen insulating and heat-resistance properties. However, like the prior art, the formation of the oxide may be eliminated. Subsequently, an impurity region is formed in the semiconductor region 704 in self-alignment.
Thereafter, an interlayer insulator 709 is formed at only a portion where second wirings are intersected. In this case, when the interlayer insulator is formed of silicon oxide, the etching proceeds to the silicon nitride layer 706, but stopped thereat, so that a flat structure is obtained. Subsequently, only the aluminum oxide or silicon nitride layer at the semiconductor region 704 and the gate oxide film (silicon oxide) beneath the aluminum oxide or silicon nitride layer are etched, so that the surface of the semiconductor region is exposed. At this time, the gate electrode is required not to be etched. Even for the aluminum electrode, sufficient corrosion resistance can be obtained when an anodic oxidation film is provided therearound.
Finally, metal wiring and electrode 710 and 711 are formed of a second metal layer. A transparent electrode may be formed for a liquid crystal display device. As is apparent from FIG. 10, the section of the element thus formed is designed so as to be as flat as that of FIG. 12.
An insulated gate field effect transistor in accordance with the present invention comprises:
source and drain regions provided on a substrate;
a conductor connected with one of said source and drain regions and provided on said substrate; and
a film provided on said substrate and in contact with said conductor and comprising a material selected from the group consisting of silicon nitride and aluminum oxide.
The conductor may comprise a metal wiring or a pixel electrode of an electro-optical device. Ratio of nitrogen to silicon in the silicon nitride film is preferably 1 to 4/3. Also, ratio of oxygen to aluminum in the aluminum oxide film is preferably 1.4 to 1.5.